Method And System For A Power Reduction Scheme For Ethernet PHYS

ABSTRACT

Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

Not Applicable.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to communication of signals.More specifically, certain embodiments of the invention relate to amethod and system for a power reduction scheme for Ethernet PHYs.

BACKGROUND OF THE INVENTION

As the number of devices connected to data networks increase and higherdata rates are required, there is a growing need for new transmissiontechnologies enabling higher transmission rates over existing coppercabling infrastructures. Various efforts exist in this regard, includingtechnologies that enable transmission rates that may even exceedGigabits-per-second (Gbps) data rates over existing cabling. Forexample, the IEEE 802.3 standard defines the (Medium Access Control) MACinterface and physical layer (PHY) for Ethernet connections at 10 Mbps,100 Mbps, 1 Gbps, and 10 Gbps data rates over twisted-pair coppercabling 100 m in length. With each 10× rate increase more sophisticatedsignal processing is required to maintain the 100 m standard cablerange. However, connections longer than 100 m may require either the useof fiber or the placement of Ethernet switches, hubs, and/or repeaters,at mid-points in the connection to keep all cables less than 100 m inlength.

Other efforts include the development of a standard for 10Gigabits-per-second (Gbps) Ethernet transmission over twisted-paircabling (10GBase-T). The emerging 10GBase-T PHY specification isintended to enable 10 Gbps connections over twisted-pair cabling atdistances of up to 182 feet for existing cabling, and at distances of upto 330 feet for new cabling, for example. To achieve full-duplextransmission at 10 Gbps over four-pair twisted-pair copper cabling,elaborate digital signal processing techniques are needed to remove orreduce the effects of severe frequency-dependent signal attenuation,signal reflections, near-end and far-end crosstalk between the fourpairs, and external signals coupled into the four pairs either fromadjacent transmission links or other external noise sources. Moreover,new cabling specifications are being developed to diminishsusceptibility to external electro-magnetic interferences.

As the operations of newer and more sophisticated Ethernet PHYs becomemore complex, one aspect that remains of importance to the user is theneed to minimize or reduce the overall power consumption of thesedevices. In this regard, novel schemes may be necessary that enablecontrolling the overall power usage of Ethernet PHYs under certainoperating conditions.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for a power reduction scheme forEthernet PHYs, substantially as shown in and/or described in connectionwith at least one of the figures, as set forth more completely in theclaims.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an Ethernet over twisted-paircabling link between a local link partner and a remote link partner, inconnection with an embodiment of the invention.

FIG. 2 is a block diagram illustrating an exemplary Ethernet transceivermulti-rate PHY layer architecture that supports power reduction schemes,in accordance with an embodiment of the invention.

FIG. 3 is a block diagram illustrating ECHO, NEXT, and FEXT channelconditions in a Gigabit Ethernet system, in connection with anembodiment of the invention.

FIG. 4 is a block diagram of an exemplary 10/100/1000Base-T Ethernetconnection operating over four-pair twisted-pair cabling, in connectionwith an embodiment of the invention.

FIG. 5 is a block diagram of an exemplary 10Base-T Ethernet connectionoperating over two-pair twisted-pair cabling, in connection with anembodiment of the invention.

FIG. 6 is a diagram illustrating exemplary signaling between linkpartners during a 10Base-T Ethernet connection, in accordance with anembodiment of the invention.

FIG. 7 is a flow diagram illustrating exemplary steps in determiningwhen to enable or disable a power reduction scheme for 10Base-T Ethernetconnections, in accordance with an embodiment of the invention.

FIG. 8 is a block diagram illustrating an exemplary Ethernettransmission system with a passive termination block utilized for apower reduction scheme, in accordance with an embodiment of theinvention.

FIG. 9 is a circuit diagram illustrating an exemplary passivetermination block, in accordance with an embodiment of the invention.

FIG. 10 is a block diagram illustrating an exemplary system with anintegrated hybrid and passive termination block utilized for a powerreduction scheme, in accordance with an embodiment of the invention.

FIG. 11 is a circuit diagram illustrating an exemplary integrated hybridand passive termination block, in accordance with an embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor a power reduction scheme for Ethernet PHYs. Aspects of the inventionmay comprise a scheme that may reduce the overall power of an EthernetPHY under certain operating conditions. Such a scheme may be utilizedwhen implementing transmitters in the Ethernet PHY that utilize atransmit digital-to-analog converter (DAC), such as a transmit voltagemode DAC (VDAC) or a transmit current mode DAC (IDAC). In someinstances, transmit VDACs may be utilized in an Ethernet PHY since theymay enable reduced power consumption when compared to transmit IDACs.However, VDACs may operate somewhat differently than IDACs regardingtheir ability to start transmitting signals after being powered down.For example, an IDAC may be able to transmit signals on the analogtransmission medium after a very short time from receiving a power-upcontrol indication. A typical time from power-up control indication tothe start of accurate analog signal transmission may be approximatelyless than 40 ns. However, in some VDAC implementations, a typical timefrom power-up control indication to the start of accurate analog signaltransmission may be well over 1 μs, and in some instances perhaps up to6 μs. In this regard, the time to power-up a VDAC may be considered whenimplementing power reduction schemes. Notwithstanding, an embodiment ofthe invention may utilize a power reduction scheme when transmit VDACsor transmit IDACs are utilized.

Aspects of the invention may comprise a power reduction scheme in anEthernet PHY in a link partner that may disable transmission via atransmit DAC during an inactive connection, 10Base-T autonegotiationoperation, and/or active 10Base-T connection with no data packettransmission. The transmit DAC may be a transmit VDAC or a transmitIDAC. The Ethernet PHY or a MAC device in the link partner may determinewhen to disable transmission via the DAC. In this regard, the EthernetPHY or the MAC device may generate appropriate signals for disabling thetransmission, The DAC may be enabled for transmission by the EthernetPHY or the MAC device when a connection becomes active or when an active10Base-T connection is ready to transmit data. Moreover, the EthernetPHY may enable transmission via the DAC when operating in a forced10Base-T mode of operation and the connection to the link partner isactive.

FIG. 1 is a block diagram illustrating an Ethernet over twisted-paircabling link between a local link partner and a remote link partner, inconnection with an embodiment of the invention. Referring to FIG. 1,there is shown a system 100 that comprises a local link partner 102 anda remote link partner 104. The local link partner 102 and the remotelink partner 104 communicate via a cable 112. The cable 112 may be a4-pair unshielded twisted-pair (UTP) copper cabling, for example.Certain performance and/or specifications criteria for UTP coppercabling have been standardized. For example, Category 3 cabling mayprovide the necessary performance for 10 Mbps Ethernet transmissionsover twisted-pair cabling (10BASE-T). In another example, Category 5cabling may provide the necessary performance for 1000 Mbps, or Gbps,Ethernet transmissions over twisted-pair cabling (1000BASE-T). In mostinstances, a lower category cable may generally have a greater insertionloss than a higher category cable.

The local link partner 102 comprises a computer system 106 a, a mediumaccess control (MAC) controller 108 a, and a transceiver 104 a. Theremote link partner 104 comprises a computer system 106 b, a MACcontroller 108 b, and a transceiver 110 b. Notwithstanding, theinvention is not limited in this regard.

The transceiver 110 a comprises suitable logic, circuitry, and/or codethat may enable communication, for example, transmission and receptionof data, between the local link partner 102 and a link partner, such asthe remote link partner 104, for example. Similarly, the transceiver 110b comprises suitable logic, circuitry, and/or code that may enablecommunication between the remote link partner 104 and a link partner,such as the local link partner 102, for example. The transceivers 110 aand 110 b may enable multi-rate communications, such as 10 Mbps, 100Mbps, 1000 Mbps (or 1 Gbps) and/or 10 Gbps, for example. In this regard,the transceivers 110 a and 110 b may support standard-based data ratesand/or non-standard data rates. The transceivers 110 a and 110 b mayutilize multilevel signaling. In this regard, the transceivers 110 a and110 b may utilize pulse amplitude modulation (PAM) with various levelsto represent the various symbols to be transmitted. For example, for1000 Mbps Ethernet applications, a PAM5 transmission scheme may beutilized in each twisted-pair wire, where PAM5 refers to PAM with fivelevels {−2, −1, 0, 1, 2}.

The data transmitted and/or received by the transceivers 110 a and 110 bmay be formatted in accordance with the well-known OSI protocolstandard. The OSI model partitions operability and functionality intoseven distinct and hierarchical layers. Generally, each layer in the OSImodel is structured so that it may provide a service to the immediatelyhigher interfacing layer. For example, layer 1, or physical (PHY) layer,may provide services to layer 2 and layer 2 may provide services tolayer 3.

The transceivers 110 a and 110 b may utilize power reduction schemes incertain operating conditions. The power saving schemes may be enabled bythe transceivers 110 a and 110 b and/or by their respective MACcontrollers 108 a and 108 b, for example. Each of the transceivers 110 aand 110 b may utilize more than one power saving scheme in accordancewith the operating conditions and/or the hardware utilized by thetransceivers 110 a and 110 b. In some instances, for example, the powerreduction schemes may be associated with the transmission of data fromone link partner to another link partner.

In the embodiment of the invention illustrated in FIG. 1, the computersystems 106 a and 106 b may represent layer 3 and above, the MACcontrollers 108 a and 108 b may represent layer 2 and above and thetransceivers 110 a and 110 b may represent the operability and/orfunctionality of layer 1 or the PHY layer. In this regard, the computersystems 106 a and 106 b comprise suitable logic, circuitry, and/or codethat may enable operability and/or functionality of the five highestfunctional layers for data packets that are to be transmitted over thecable 112. Since each layer in the OSI model provides a service to theimmediately higher interfacing layer, the MAC controllers 108 a and 108b may provide the necessary services to the computer systems 106 a and106 b to ensure that packets are suitably formatted and communicated tothe transceivers 110 a and 110 b. During transmission, each layer addsits own header to the data passed on from the interfacing layer aboveit. However, during reception, a compatible device having a similar OSIstack strips off the headers as the message passes from the lower layersup to the higher layers.

The transceivers 110 a and 110 b may be configured to handle all thephysical layer requirements, which include, but are not limited to,packetization, data transfer and serialization/deserialization (SERDES),in instances where such an operation is required. Data packets receivedby the transceivers 110 a and 110 b from MAC controllers 108 a and 108b, respectively, may include data and header information for each of theabove six functional layers. The transceivers 110 a and 110 b may beconfigured to encode data packets that are to be transmitted over thecable 112 and/or to decode data packets received from the cable 112.

The MAC controller 108 a comprises suitable logic, circuitry, and/orcode that may enable handling of data link layer, layer 2, operabilityand/or functionality in the local link partner 102. Similarly, the MACcontroller 108 b comprises suitable logic, circuitry, and/or code thatmay enable handling of layer 2 operability and/or functionality in theremote link partner 104. The MAC controllers 108 a and 108 b may beconfigured to implement Ethernet protocols, such as those based on theIEEE 802.3 standard, for example. The MAC controllers 108 a and 108 bmay enable power reduction schemes when certain operating conditions aredetected. Notwithstanding, the invention is not limited in this regard.

The MAC controller 108 a may communicate with the transceiver 110 a viaan interface 114 a and with the computer system 106 a via a buscontroller interface 116 a. The MAC controller 108 b may communicatewith the transceiver 110 b via an interface 114 b and with the computersystem 106 b via a bus controller interface 116 b. The interfaces 114 aand 114 b may correspond to Ethernet interfaces that comprise protocoland/or link management control signals. The interfaces 114 a and 114 bmay be multi-rate interfaces. The bus controller interfaces 116 a and116 b may correspond to PCI or PCI-X interfaces. The interfaces 114 aand 114 b may be utilized in some instances to communicate informationassociated with power reduction schemes to be implemented on thetransceivers 110 a and 100 b when certain operating conditions aredetected. Notwithstanding, the invention is not limited in this regard.

FIG. 2 is a block diagram illustrating an exemplary Ethernet transceivermulti-rate PHY layer architecture, in accordance with an embodiment ofthe invention. Referring to FIG. 2, there is shown a link partner 200that comprises a transceiver 202, a MAC controller 204, a computersystem 206, an interface 208, and a bus controller interface 210. Thetransceiver 202 may be an integrated device that comprises a multi-ratePHY block 212, a plurality of transmitters 214 a, 214 c, 214 e, and 214g, a plurality of receivers 214 b, 214 d, 214 f, and 214 h, a memory216, and a memory interface 218. The operation of the transceiver 202may be the same as or substantially similar to the transceivers 110 aand 110 b as described in FIG. 1. In this regard, the transceiver 202may provide layer 1 or PHY layer operability and/or functionality.Similarly, the operation of the MAC controller 204, the computer system206, the interface 208, and the bus controller 210 may be the same as orsubstantially similar to the respective MAC controllers 108 a and 108 b,computer systems 106 a and 106 b, interfaces 114 a and 114 b, and buscontroller interfaces 116 a and 116 b as described in FIG. 1. The MACcontroller 204 may comprise a multi-rate interface 204 a that maycomprise suitable logic, circuitry, and/or code to enable communicationwith the transceiver 202 at a plurality of data rates via the interface208.

The multi-rate PHY block 212 in the transceiver 202 comprises suitablelogic, circuitry, and/or code that may enable operability and/orfunctionality of PHY layer requirements. The multi-rate PHY block 212communicates with the MAC controller 204 via the interface 208. In oneaspect of the invention, the interface 208 may be configured to utilizea plurality of serial data lanes for receiving data from the multi-ratePHY block 212 and/or for transmitting data to the multi-rate PHY block212, in order to achieve higher operational speeds such as Gbps or 10Gbps, for example. The multi-rate PHY block 212 may be configured tooperate in one or more of a plurality of communication modes, where eachcommunication mode implements a different communication protocol. Thesecommunication modes may include, but are not limited to, IEEE 802.3,10GBase-T and other similar protocols. For example, the multi-rate PHYblock 212 may support 10Base-T, 100Base-T, 1000Base-T, and/or 10GBase-Toperation. The multi-rate PHY block 212 may be configured to operate ina particular mode of operation upon initialization or during operation.

The multi-rate PHY block 212 may also be configured to operate in otheroperating modes, such as an extended range mode that may support cablelengths that are longer than those supported by standard modes. In someinstances, an auto-negotiation scheme may be utilized by the transceiver202 to indicate or communicate to a remote link partner that thetransceiver 202 is operating in a particular mode. The remote linkpartner may then configure itself to the appropriate mode. In someinstances, through standard auto-negotiation, a network link may beconfigured as an extended range from only one end of the link, ensuringinteroperability between extended range enabled Ethernet transceiversand legacy or standard devices. In some instances, the link may bepre-configured and the transceivers fixed in an extended range mode.

The multi-rate PHY block 212 may be coupled to memory 216 through thememory interface 218, which may be implemented as a serial interface ora bus. The memory 216 comprises suitable logic, circuitry, and/or codethat may enable storage or programming of information that includesparameters and/or code that may effectuate the operation of themulti-rate PHY block 212. The parameters may comprise configuration dataand the code may comprise operational code such as software and/orfirmware, but the information need not limited in this regard. Moreover,the parameters may include adaptive filter and/or block coefficients foruse by the multi-rate PHY block 212, for example.

The transmitters 214 a, 214 c, 214 e, and 214 g may comprise suitablelogic, circuitry, and/or code that may enable transmission of data fromthe link partner 200 to a remote link partner via the cable 212 in FIG.1, for example. In this regard, the transmitters 214 a, 214 c, 214 e,and 214 g may be implemented using digital-to-analog converters (DACs).For example, transmitters 214 a, 214 c, 214 e, and 214 g may beimplemented using voltage-controlled or voltage mode DACs (VDACs) orcurrent-controlled or current mode DACs (IDACs) to enable reduced powerconsumption operation. The DACs may be utilized to convert digitalsignals received from the multi-rate PHY block 212 into analog signalsfor transmission over a twisted-pair wire, for example. Moreover, powerreduction schemes or modes may also be utilized to enable or disable theDACs integrated within the transmitters 214 a, 214 c, 214 e, and 214 gduring the appropriate operating conditions to further reduce theoverall power consumption of the Ethernet transceiver 202. In someinstances, at least one signal may be generated by the Ethernettransceiver 202 and/or the MAC controller 204 to enable or disable theoperation of DACs integrated into the transmitters 214 a, 214 c, 214 e,and 214 g. In this regard, each of the transmitters 214 a, 214 c, 214 e,and 214 g may be controlled separately when enabling or disabling DACsfor power reduction operations.

The receivers 214 b, 214 d, 214 f, and 214 h may comprise suitablelogic, circuitry, and/or code that may enable receiving data from aremote link partner by the link partner 200. Each of the four pairs oftransmitters and receivers in the transceiver 202 correspond to one ofthe four wires in the cable 212. For example, transceiver 214 a andreceiver 214 b are utilized to communicate with a remote link partnervia the first wire pair in the cable 212. Similarly, transceiver 214 gand receiver 214 h may be utilized to communicate with a remote linkpartner via the fourth wire pair in the cable 212. In this regard, atleast one of the four transceiver/receiver pairs may be enabled toprovide the appropriate communication rate.

FIG. 3 is a block diagram illustrating ECHO, NEXT, and FEXT channelconditions in a Gigabit Ethernet (1GBase-T) system, in connection withan embodiment of the invention. Referring to FIG. 3, there is shown aGigabit Ethernet system 300 that may comprise a local link partner 301 aand a remote link partner 301 b. The local link partner 301 a and theremote link partner 301 b may communicate via four twisted-pair wires310 in full duplex operation. Each of the four twisted-pair wires 310may support 250 Mbps data rates to provide an aggregate data rate of 1Gbps. The local link partner 301 a may comprise four hybrids 306. Eachhybrid 306 in the local link partner 301 a may be communicativelycoupled to a transmitter 302, a receiver 304, and to one of the fourtwisted-pair wires 310. Similarly, the remote link partner 301 b maycomprise four hybrids 306. Each hybrid 306 in the remote link partner301 b may be communicatively coupled to a transmitter 302, a receiver304, and to one of the four twisted-pair wires 310. The portions of thelocal link partner 301 a and the remote link partner 301 b shown in FIG.3 may correspond to a portion of the physical (PHY) layer operationssupported by the local link partner 301 a and remote link partner 301 brespectively.

Each hybrid 306 in the local link partner 301 a or the remote linkpartner 301 b may be communicatively coupled to or comprise atransformer 308. The hybrid 306 may comprise suitable logic, circuitry,and/or code that may enable separating the transmitted and receivedsignals from a twisted-pair wire 310. The transmitters 302 may comprisesuitable logic, circuitry, and/or code that may enable generatingsignals to be transmitted to a link partner at the other end of the linkvia a hybrid 306 and a twisted-pair wire 310. The transmitters 302 mayutilize VDACs or IDACs for converting digital signals to analog signalsfor transmission. In this regard, the VDACs or IDACs in the transmitters302 may be enabled or disabled in accordance with power reduction modesor schemes that may be implemented based on the operating conditions.The receivers 304 may comprise suitable logic, circuitry, and/or codethat may enable processing signals received from a link partner at theother end of the link via a twisted-pair wire 310 and a hybrid 306.

During operation, several conditions may occur in each of thetwisted-pair wires 310. For example, intersymbol interference (ISI) mayoccur as a result of frequency dependent wire attenuation. As shown inFIG. 3, an ECHO component may be received in a twisted-pair wire 310from an echo that results from the local transmitter 302 on the sametwisted-pair wire 310. A near-end crosstalk (NEXT) component may also bereceived in a twisted-pair wire 310 from the local transmitters 302corresponding to the three adjacent twisted-pair wires 310 in the samelink partner. Moreover, a far-end crosstalk (FEXT) component may also bereceived in a twisted-pair wire 310 from the remote transmitters 302 inthe link partner at the other end of the link.

Since a Gigabit Ethernet system, such as the Gigabit Ethernet system300, for example, may require fast operation and a significant amount ofsignal processing to address at least the channel conditions illustratedin FIG. 3, power reduction modes that enable and disable DACs integratedinto the transmitters 302 may not provide sufficiently fast power-ontime to be effective with current DAC technology. However, as advancesin design and fabrication processes enable faster DAC power-onoperations, power reduction schemes that are based on the use of DACs intransmitters may be implemented in Ethernet systems operating at highcommunication rates, such as 100 Mbps or higher, for example.

FIG. 4 is a block diagram of an exemplary 10/100/1000Base-T Ethernetconnection operating over four-pair twisted-pair cabling, in connectionwith an embodiment of the invention. Referring to FIG. 4, there is showna multi-rate Ethernet system 400 that may support full duplex operationsat 10 Mbps, 100 Mbps, and/or 1000 Mbps, or Gbps. The multi-rate Ethernetsystem 400 may comprise a local link partner 401 a and a remote linkpartner 401 b. The local link partner 401 a and the remote link partner401 b may communicate via four twisted-pair wires 310 in full duplexoperation. Each of the four twisted-pair wires 310 may support2.5/25/250 Mbps data rates to provide an aggregate data rate of10/100/1000 Mbps. In this regard, the local link partner 401 a and theremote link partner 401 b may support 10Base-T, 100Base-T, and/or1000Base-T operations.

In an exemplary embodiment of the invention, the local link partner 401a may comprise four hybrids 402. The operation of the hybrid 402 may bethe same or substantially similar in operation to the hybrid 306 in FIG.3. Notwithstanding, the invention is not so limited and may supportvarious implementations of a hybrid circuitry. Each hybrid 402 in thelocal link partner 401 a may be communicatively coupled to a transmitter302, a receiver 304, and to one of the four twisted-pair wires 310. Thetransmitters 302 may be implemented utilizing DACs for conversion ofdigital signals to analog signals for transmission over a twisted-pairwire. In this regard, the DACs in the transmitters 302 may be disabledor enabled in accordance with power reduction modes or schemes whencertain operating conditions are detected. For example, the powerreduction modes or schemes may be supported by at least one of thesupported rates, such as 10Base-T, 100Base-T, and/or 1000Base-Toperations.

Associated with each hybrid 402 in the local link partner 401 a are alsoan echo canceller 404 a and a subtractor 406 a. In this regard, theoperations of the echo canceller 404 a and the subtractor 406 a maydepend on whether the local link partner 401 a is operating in 10Base-T,100Base-T, or 1000Base-T. For example, at different communication ratesor speeds different signal processing algorithms may be utilized toperform ECHO component cancellation. The local link partner 401 a mayalso comprise a demultiplexer (demux) 408 a, an aligner 410 a, and amultiplexer (mux) 412 a.

Similarly, the remote link partner 401 b may comprise four hybrids 402.Each hybrid 402 in the remote link partner 401 b may be communicativelycoupled to a transmitter 302, a receiver 304, and to one of the fourtwisted-pair wires 310. Associated with each hybrid 402 in the remotelink partner 401 b are also an echo canceller 404 b and a subtractor 406b. The remote link partner 401 b may also comprise a demux 408 b, analigner 410 b, and a mux 412 b. The portions of the local link partner401 a and remote link partner 401 b shown in FIG. 4 may correspond to aportion of the physical (PHY) layer operations supported by the locallink partner 401 a and remote link partner 401 b respectively.

The demuxes 408 a and 408 b may comprise suitable logic, circuitry,and/or code that may enable separating a 10 Mbps, 100 Mbps, or 1 Gbpssignal respectively into four 2.5 Mbps, 25 Mbps, or 250 Mbps signals fortransmission over the four twisted-pair wires. The aligners 410 a and410 b may comprise suitable logic, circuitry, and/or code that mayenable aligning the 2.5 Mbps, 25 Mbps, or 250 Mbps signals received fromeach of the four twisted-pair wires. The muxes 412 a and 412 b maycomprise suitable logic, circuitry, and/or code that may enablecombining the aligned 2.5 Mbps, 25 Mbps, or 250 Mbps signals from thealigners 410 a and 410 b to generate a 10 Mbps, 100 Mbps, or 1 Gbpsreceived signal.

The echo cancellers 404 a and 404 b may comprise suitable logic,circuitry, and/or code that may enable processing the signal to betransmitted via a transmitter 302 to cancel or otherwise mitigate theECHO component in the corresponding signal received via the receiver 304associated with the same twisted-pair wire. The subtractors 406 a and406 b may comprise suitable logic, circuitry, and/or code that mayenable canceling or mitigating the ECHO component from the receivedsignal.

In an exemplary embodiment of the invention, in operation, the locallink partner 401 b may separate a 10 Mbps, 100 Mbps, or 1000 Mbps signalto be transmitted into four 2.5 Mbps, 25 Mbps, or 250 Mbps signals viathe demux 408 a. Each signal to be transmitted may be processed by thetransmitter 302 before being communicated to the correspondingtwisted-pair wire via a hybrid 402. The four transmitted signals mayarrive at the remote link partner 401 b where each may be processed by areceiver 404 before an appropriate ECHO component cancellation operationoccurs from the operation of a corresponding echo canceller 404 b andsubtractor 406 b. The four received 2.5 Mbps, 25 Mbps, or 250 Mbpssignals may be aligned in the aligner 410 b before being combined in themux 412 b into a 10 Mbps, 100 Mbps, or 1000 Mbps received signal.

Similarly, in another exemplary embodiment of the invention, inoperation, the remote link partner 401 b may separate a 10 Mbps, 100Mbps, or 1000 Mbps signal to be transmitted into four 2.5 Mbps, 25 Mbps,or 250 Mbps signals via the demux 408 b. Each signal to be transmittedmay be processed by a transmitter 302 before being communicated to thecorresponding twisted-pair wire via a hybrid 402. The four transmittedsignals may arrive at the local link partner 401 a where each may beprocessed by a receiver 304 before an appropriate ECHO componentcancellation operation occurs from the operation of a corresponding echocanceller 404 a and subtractor 406 a. The four received 2.5 Mbps, 25Mbps, or 250 Mbps signals may be aligned in the aligner 410 a beforebeing combined in the mux 412 a into a 10 Mbps, 100 Mbps, or 1000 Mbpsreceived signal.

FIG. 5 is a block diagram of an exemplary 10Base-T Ethernet connectionoperating over two-pair twisted-pair cabling, in connection with anembodiment of the invention. Referring to FIG. 5, there is shown amulti-rate Ethernet system 500 operating as a 10Base-T connection thatsupports a 10 Mbps rate over two-pair twisted-pair wire. The multi-rateEthernet system 500 may also support other modes of operation, such as100 Mbps and/or 1000 Mbps rates over two-pair twisted-pair wire. Themulti-rate Ethernet system 500 may comprise a local link partner 501 aand a remote fink partner 501 b. The local link partner 501 a and theremote link partner 501 b may communicate via two twisted-pair wires 310in full duplex operation at 5 Mbps at each wire to provide an aggregatedata rate of 10 Mbps. The local link partner 501 a may utilize twohybrids 402 with corresponding echo canceller 404 a and a subtractor 406a. The local link partner 501 a may also utilize a demux 408 a, analigner 410 a, and a mux 412 a for transmission and reception of signalsat the communication rate of 10 Mbps. Similarly, the remote link partner501 b may utilize two hybrids 402 with corresponding echo canceller 404b and a subtractor 406 b. The remote link partner 501 b may also utilizea demux 408 b, an aligner 410 b, and a mux 412 b for transmission andreception of signals at the reduced communication rate of 10 Mbps. Thetwo remaining twisted-pair wires remain unused.

In one embodiment of the invention, when a multi-rate Ethernet system,such as the multi-rate Ethernet system 500, for example, operates as a10Base-T connection as shown, the multi-rate Ethernet system 500 maysupport power reduction modes or schemes that appropriately enable ordisable DACs integrated into the transmitters 302 in either the locallink partner 501 a and the remote link partner 501 b. In this regard,the power reduction schemes may be based on operating conditionsassociated with the operation of the multi-rate Ethernet system 500 as a10Base-T connection, for example.

When implementing power reduction modes or schemes based on disabling orpowering down DACs in the transmitters in an Ethernet PHY, considerationmay be given to the type of signaling produced by the Ethernet PHY for aparticular connection rate.

FIG. 6 is a diagram illustrating exemplary signaling between linkpartners during a 10Base-T Ethernet connection, in accordance with anembodiment of the invention. Referring to FIG. 6, there is shown asignal 600 communicated from an Ethernet PHY over a 10Base-T connection.The signal 600 may comprise a plurality of link pulses 602, a pluralityof data packets 606, and a plurality of idle portions 604. In thisregard, power reduction schemes or modes that power down or disable DACsin transmitters within the Ethernet PHY may be utilized in 10Base-Tconnections because the signaling scheme utilizes the idle portions 604on the transmission medium for sufficiently long periods of time. Sincethe idle portions 604 need not comprise information and occur betweenthe data packets 606 and/or between link pulses 602, powering down theDACs in the transmitters may not affect the transfer of informationbetween the Ethernet PHY and the remote link partner.

FIG. 7 is a flow diagram illustrating exemplary steps in determiningwhen to enable or disable a power reduction scheme for 10Base-T Ethernetconnections, in accordance with an embodiment of the invention.Referring to FIG, 7, there is shown a flow diagram 700. In step 704,after start step 702, when the Ethernet PHY controls or determineswhether a power reduction scheme is to be implemented that disables atleast a portion of a DAC integrated into a transmitter within theEthernet PHY, then the process may proceed to step 712. In step 712,when the Ethernet PHY is operating in a forced 10Base-T mode and thelink with a remote device is active, the process may proceed to step720. In step 720, the Ethernet PHY may generate signals that maymaintain the DACs enabled while in the forced 10Base-T mode.

Returning to step 712, when the Ethernet PHY is not operating in aforced 10Base-T mode with an active link to a remote device, the processmay proceed to step 714. In step 714, the Ethernet PHY may generate atleast one signal that may disable at least a portion of a DAC integratedinto a transmitter within the Ethernet PHY when at least one of thefollowing occurs: the link with the remote partner may be down or notactive and the Ethernet PHY may currently be operating in anautonegotiation mode. In step 716, in instances when the 10Base-Tconnection may be active and ready to transmit data, the process mayproceed to step 718. In step 718, the Ethernet PHY may generate at leastone signal that may enable a DAC integrated in a transmitter within theEthernet PHY. In instances when the 10Base-T connection may not beactive and ready to transmit data, the Ethernet PHY may continue tomonitor the connection until it becomes active and is ready to transmitdata.

Returning to step 704, when the MAC controls or determines whether apower reduction scheme is to be implemented that disables at least aportion of a DAC integrated into a transmitter within the Ethernet PHY,then the process may proceed to step 706. In step 706, the MAC maygenerate at least one signal that may disable at least a portion of aDAC integrated into a transmitter within the Ethernet PHY when at leastone of the following occurs: the link with the remote partner is down ornot active and the Ethernet PHY connection is active but nottransmitting data packets. In step 708, in instances when the 10Base-Tconnection may be active and ready to transmit data, the process mayproceed to step 710. In step 718, the MAC may generate at least onesignal that may enable a DAC integrated into a transmitter within theEthernet PHY. In instances when the 10Base-T connection may not beactive and ready to transmit data, the MAC may continue to monitor theconnection until it becomes active and is ready to transmit data.

The above described scheme may not apply to transmission modes, such ascurrent implementations of 100Base-TX and 1000Base-T modes of operation,where encoders and scramblers may be used at all times, requiring thatthe DAC in the transmitter be continuously active to enable transmittinganalog signals over the media. In this regard, the DAC may be placedinto a reduced power mode for these transmission modes when the linkbecomes inactive.

In an embodiment of the invention, power reduction modes or schemes maybe implemented in Ethernet PHYs that utilize DACs in their transmittersand that are integrated in battery-operated devices such as a laptopcomputer and/or a wireless device, for example. For example, theEthernet PHY may be frequently not linked to a wired network when thedevice is running on battery power and the use of power reduction modesmay be one mechanism for the device to save power in such instances.

In another aspect of the invention, Ethernet standards may require thatthe analog interface to a transmission medium presents a substantiallystable or constant termination impedance. For example, correct operationat 10 Mbps, 100 Mbps and 1 Gbps Ethernet speeds via twisted-pair wiresmay require termination with a 100 ohm impedance. This may beaccomplished passively with a resistor or actively with a transistorcircuit, for example. However, when power to a DAC is turned off ordisabled, the termination impedance may no longer be kept at the desiredvalue or range of values. In this regard, DACs utilized in Ethernet PHYsthat support power reduction modes may comprise or be integrated with,for example, a bypass-impedance that may be switched into place at theanalog interface when the DAC is powered down and the active impedanceon the line is removed.

FIG. 8 is a block diagram illustrating an exemplary Ethernettransmission system with a passive termination block utilized for apower reduction scheme, in accordance with an embodiment of theinvention. Referring to FIG. 8, there is shown a 1 Gigabit (1G) driver802 and 10 Mbps driver 804, a hybrid 806, pads 810 a and 810 b, and apassive termination 808. The 1G driver 802 may comprise suitable logic,circuitry, and/or code that may be utilized to transmit signals at 1Gbps in accordance with Ethernet standards. The 10 Mbps driver 804 maycomprise suitable logic, circuitry, and/or code that may be utilized totransmit signals at 10 Mbps in accordance with Ethernet standards. Thehybrid 806 may comprise suitable logic, circuitry, and/or code that maybe utilized to couple the signals generated by the 1G driver 802 to ananalog output line, such as a twisted-pair wire, for example. The pads810 a and 810 b may comprise suitable logic and/or circuitry that mayenable coupling an analog output line to the passive termination 808.The passive termination 808 may comprise suitable logic, circuitry,and/or code that may enable switching on a bypass impedance in parallelwith the pads 810 a and 810 b when DACs in the 1G driver 802 and/or inthe 10 Mbps driver 804 are powered down in accordance with a powerreduction scheme, for example. In this regard, switching the passivetermination 808 on between the pads 810 a and 810 b may provide theappropriate impedance matching termination as required by the Ethernetstandards.

FIG. 9 is a circuit diagram illustrating an exemplary passivetermination block, in accordance with an embodiment of the invention.Referring to FIG. 9, there is shown a passive termination 900 comprisinga resistor 902, transistors 904, 906, and 908, resistors 910 a and 910b, and pads 912 a and 912 b. The transistors 904, 906, and 908 may beNMOS FETs, for example. When the passive termination 900 is switched onas disclosed in FIG. 8, the resistors 910 a and 910 b may provide theparallel impedance matching termination needed for the analog outputline. For example, each of the resistors 910 a and 910 b may be 50 ohmsto provide an aggregate 100 ohm termination. This may be implemented byutilizing the transistor 908 as a switch. The resistor 902 between Vddand Gnd may be utilized to provide a Vdd/2 bias voltage to thetransistor 908 via the transistors 904 and 906 so that the transistor908 perceives very little voltage movement and a transmission gateswitch may not be necessary. In this regard, the power consumed by thepassive termination 900 is mostly the power consumed by the resistor 902between Vdd and Gnd. The passive termination 900 disclosed in FIG. 9 maybe implemented utilizing a plurality of CMOS processing technologies,for example.

FIG. 10 is a block diagram illustrating an exemplary system with anintegrated hybrid and passive termination block utilized for a powerreduction scheme, in accordance with an embodiment of the invention.Referring to FIG. 10, there is shown the 1G driver 802, the 10 Mbpsdriver 804, the pads 810 a and 810 b, and a hybrid and passivetermination 1002. In this regard, the hybrid and passive termination1002 may comprise suitable logic, circuitry, and/or code that may enableswitching on a bypass impedance in parallel with the pads 810 a and 810b when DACs in the 1G driver 802 and/or in the 10 Mbps driver 804 arepowered down in accordance with a power reduction scheme, for example.Moreover, the hybrid and passive termination 1002 may comprise anintegrated hybrid circuitry that may enable coupling the signalsgenerated by the 1G driver 802 to an analog output line, such as atwisted-pair wire, for example. In this regard, switching the hybrid andpassive termination 1002 on between the pads 810 a and 810 b may providethe appropriate impedance matching termination as required by theEthernet standards.

FIG. 11 is a circuit diagram illustrating an exemplary integrated hybridand passive termination block, in accordance with an embodiment of theinvention. Referring to FIG. 11, there is shown a hybrid and passivetermination 1100 comprising a resistors 902, 910 a, 910 b, 1102, 1108,1110, 1112, 1114, and 1116, transistors 904, 906, and 908, amplifiers1104 and 1106, and pads 912 a and 912 b. The operation of the resistors902, 910 a, 910 b, and transistors 904, 906, 908 may be to provide apassive termination impedance that matches that of the analog lineoutput as disclosed in FIG. 9. The resistors 1102, 1108, 1110, 1112,1114, and 1160, and the amplifiers 1104 and 1106 may enable the hybridoperation. In this regard, the resistors 910 a and 910 b may each be 50ohms and may be common to the hybrid operation and to the passiveimpedance matching termination. Moreover, when the resistors 1110 and1112 are 2K ohms and the resistors 1114 and 1116 are 1K ohms, forexample, the transfer function from received signal from pads to Rxinput may be ⅔. In the implementation disclosed in FIG. 9 these nodesmay be high impedance since the amplifiers are off and the switch islocated in a separate block. The transfer function from received signalfrom pads to Rx input in FIG. 9 is then ⅓. A gain factor of 2 may beachieved in the received transfer function when integrating the passivetermination with the hybrid as disclosed in FIG. 11. The hybrid andpassive termination 1100 disclosed in FIG. 11 may be implementedutilizing a plurality of CMOS processing technologies, for example.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputer system, or in a distributed fashion where different elementsare spread across several interconnected computer systems. Any kind ofcomputer system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1-35. (canceled)
 36. A method of disabling transmission of signals by anEthernet PHY, the method comprising: disabling a transmitdigital-to-analog converter (DAC) integrated within said Ethernet PHYduring one or more of the following modes of operation: inactiveconnection mode, 10Base-T autonegotiation mode, and active 10Base-Tconnection with no data packet transmission mode; and enabling a passiveimpedance termination block across an output line of said DAC.
 37. Themethod of claim 36, wherein said transmit DAC is one of a transmitvoltage mode DAC (VDAC) and a transmit current mode DAC (IDAC).
 38. Themethod of claim 36, comprising determining in a MAC device when toenable said disabling of said transmission for said Ethernet PHY. 39.The method of claim 38, comprising generating at least one signal withinsaid MAC device to enable said disabling of said transmission for saidEthernet PHY.
 40. The method of claim 36, comprising determining in saidEthernet PHY when to enable said disabling of said transmission for saidEthernet PHY.
 41. The method of claim 40, comprising generating at leastone signal within said Ethernet PHY to enable said disabling of saidtransmission for said Ethernet PHY.
 42. The method of claim 40,comprising enabling transmission for said Ethernet PHY when saidEthernet PHY is operating in a forced 10Base-T mode of operation and aconnection to a link partner is active.
 43. The method of claim 36,comprising enabling transmission for said Ethernet PHY when data packetsare available for transmission via an active 10Base-T connection. 44.The method of claim 36, wherein said enabling said passive impedancetermination block provides a substantially zero voltage differentialacross said output line of said DAC.
 45. The method of claim 36, whereinsaid enabling said passive impedance termination block is performed viaone or more transistors within said passive impedance termination block.46. A system comprising: an Ethernet PHY in a link partner, said linkpartner configured to disable transmission of signals by said EthernetPHY by: disabling a transmit digital-to-analog converter (DAC)integrated within said Ethernet PHY during one or more of the followingmodes of operation: inactive connection mode, 10Base-T autonegotiationmode, and active 10Base-T connection with no data packet transmissionmode; and enabling a passive termination block across an output line ofsaid DAC.
 47. The system of claim 46, wherein said transmit DAC is oneof a transmit voltage mode DAC (VDAC) and a transmit current mode DAC(IDAC).
 48. The system of claim 46, wherein said link partner comprisesa MAC device that enables determining when to enable said disabling ofsaid transmission for said Ethernet PHY.
 49. The system of claim 48,wherein said MAC device enables generation of at least one signal toenable said disabling of said transmission for said Ethernet PHY. 50.The system of claim 46, wherein said Ethernet PHY enables determiningwhen to enable said disabling of said transmission for said EthernetPHY.
 51. The system of claim 50, wherein said Ethernet PHY enablesgeneration of at least one signal to enable said disabling of saidtransmission for said Ethernet PHY.
 52. The system of claim 50, whereinsaid Ethernet PHY enables transmission for said Ethernet PHY when saidEthernet PHY is operating in a forced 10Base-T mode of operation and aconnection to a link partner is active.
 53. The system of claim 46,wherein said Ethernet PHY enables transmission for said Ethernet PHYwhen data packets are available for transmission via an active 10Base-Tconnection.
 54. The system of claim 46, wherein said enabling saidpassive impedance termination block provides a substantially zerovoltage differential across said output line of said DAC.
 55. The systemof claim 46, wherein said enabling said passive impedance terminationblock is performed via one or more transistors within said passiveimpedance termination block.